1 ps8355a 11/23/98 product description pericom semiconductor?s pi74alvtc series of logic circuits are produced in the company?s advanced 0.35 micron cmos technology, achieving industry leading speed. the pi74alvtc16373 is particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. this device can be used as two 8-bit latches or one 16-bit latch. when the latch enable (le) input is high, the q outputs follow the (d) inputs. when le is taken low, the q outputs are latched at the levels set up at the d inputs. a buffered output enable (oe) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state in which the outputs neither load nor drive the bus lines significantly. the high-impedance state and the increased drive provide the capability to drive bus lines without an interface or pullup components. oe does not affect internal operations of the latch. old data can be retained or new data can be entered while the ouputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to vdd through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. the family offers both i/o tolerant, which allows it to operate in mixed 1.8/3.6v systems, and ?bus hold,? which retains the data input?s last state whenever the data input goes to high-impedance, preventing ?floating? inputs and eliminating the need for pullup/ down resistors. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product features ? pi74alvtc family is designed for low voltage operation, v dd = 1.8v to 3.6v ? supports live insertion ? 3.6v i/o tolerant inputs and outputs ? bus hold ? high drive, -32/64ma @ 3.3v ? uses patented noise reduction circuitry ? power-off high impedance inputs and outputs ? industrial operation at ?40c to +85c ? packages available: ? 48-pin 240 mil wide plastic tssop (a) ? 48-pin 173 mil wide plastic tvsop (k) ? 48-pin 300 mil wide plastic ssop (v) pi74alvtc16373 16-bit transparent d-type latch with 3-state outputs logic block diagram 1le 1q1 1d c1 1d1 to seven other channels 1oe 1 48 47 2 2le 2q1 1d c1 2d1 to seven other channels 25 36 13 24 2oe
2 ps8355a 11/23/98 pi74alvtc16373 16-bit transparent d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 product pin description truth table (1) note: 1. h = high signal level l = low signal level x = don?t care or irrelevant z = high impedance product pin configuration 1 oe 1 q 1 1 q 2 gnd 1 q 3 1 q 4 v cc 1 q 5 1 q 6 gnd 1 q 7 1 q 8 2 q 1 2 q 2 gnd 2 q 3 2 q 4 v cc 2 q 5 2 q 6 gnd 2 q 7 2 q 8 2 oe 1 2 3 4 5 6 7 8 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 32 31 30 29 28 27 26 25 1 le 1 d 1 1 d 2 gnd 1 d 3 1 d 4 v cc 1 d 5 1 d 6 gnd 1 d 7 1 d 8 2 d 1 2 d 2 gnd 2 d 3 2 d 4 v cc 2 d 5 2 d 6 gnd 2 d 7 2 d 8 2 le 48-pin a48 k48 v48 pin name description o e output enable input (active low) l e latch enable (active high) d x data inputs q x 3-state outputs gnd ground v cc power s t u p n i ) 1 ( s t u p t u o ) 1 ( e oe ld q lh h h lh l l ll x q o hx x z
3 ps8355a 11/23/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvtc16373 16-bit transparent d-type latch with 3-state outputs note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. supply voltage range, v dd .......................................... C0.5v to 4.6v input voltage range, v i ................................................. -0.5v to 4.6v output voltage range, v o (3-stated) ............................ -0.5v to 4.6v output voltage range, v o (1) (active) ................. C0.5v to v dd +0.5v dc input diode current (i ik ) v i <0v ........................................ -50ma dc output diode current (i ok ) v o <0v ................................................................................... -50ma v o >v dd ................................................................................ 50ma dc output source/sink current (i oh /i ol ) ......................... -64/128ma dc v dd or gnd current per supply pin (i cc or gnd) ....... 100ma storage temperature range, t stg ................................. C65 c to150 c recommended operating conditions 2 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) notes 1. absolute maximum of i o must be observed. 2. unused control inputs must be held high or low to prevent them from floating. 3 as measured between 0.8v and 2.0v, v dd = 3.0v. . n i m. x a ms t i n u v d d e g a t l o v y l p p u s g n i t a r e p o8 . 16 . 3 v y l n o n o i t n e t e r a t a d2 . 16 . 3 v h i e g a t l o v t u p n i l e v e l - h g i hv d d v 6 . 3 o t v 7 . 2 =0 . 2 v l i e g a t l o v t u p n i l e v e l - w o lv d d v 6 . 3 o t v 7 . 2 =8 . 0 v i e g a t l o v t u p n i3 . 0 -6 . 3 v o e g a t l o v t u p t u o e t a t s e v i t c a0v d d e t a t s f f o06 . 3 i n i t n e r r u c t u p t u o h o i / l o v d d v 6 . 3 o t v 0 . 3 = v d d v 6 . 3 o t v 0 . 3 = v d d v 7 . 2 o t v 3 . 2 = v d d v 8 . 1 = 4 6 / 2 3 - 4 2 8 1 6 a m d / t d v e t a r l l a f r o e s i r n o i t s i s n a r t t u p n i ) 3 ( 00 1v / s n t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o - 0 4 5 8c
4 ps8355a 11/23/98 pi74alvtc16373 16-bit transparent d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) dc characteristics (2.7v 5 ps8355a 11/23/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvtc16373 16-bit transparent d-type latch with 3-state outputs dc characteristics (2.3v v dd 2.7v) n o i t p i r c s e ds r e t e m a r a ps n o i t i d n o cv d d . n i m. p y t. x a ms t i n u v h i e g a t l o v t u p n i l e v e l h g i h 7 . 2 - 3 . 2 6 . 1 v v l i e g a t l o v t u p n i l e v e l w o l 7 . 0 v h o e g a t l o v t u p t u o l e v e l h g i h i h o 0 0 1 - = m av d d 2 . 0 - i h o a m 2 1 - = 3 . 2 8 . 1 i h o a m 8 1 - =7 . 1 v l o e g a t l o v t u p t u o l e v e l w o l 7 . 2 - 3 . 22 . 0 i l o a m 2 1 = 3 . 2 4 . 0 i l o a m 8 1 =5 . 0 i l o a m 4 2 =5 5 . 0 i i t n e r r u c e g a k a e l t u p n iv i v = d d d n g r o7 . 20 . 5 m a i z o e g a k a e l t u p t u o e t a t s - 3v o 6 . 3 = v3 . 20 1 i f f o t n e r r u c e g a k a e l f f o - r e w o pv i v r o o 6 . 3 v0 0 1 i l d o w o l t n e r r u c t u p t u ov n i = v h i r ov , l i v o =v 5 . 1 ) 2 ( 7 . 2 0 1 14 6 2 a m i h d o h g i h t n e r r u c t u p t u ov n i = v h i r ov , l i v o =v 5 . 1 ) 2 ( 0 3 -0 6 - i d l o h ) 1 ( t n e r r u c d l o h s u b s t u p t u o b r o a v i v 7 . 0 = 5 . 2 0 9 m a v i v 7 . 1 =0 9 - i d d t n e r r u c y l p p u s t n e c s e i u q v i v = d d d n g r o 7 . 2 - 3 . 2 0 4 v d d v ( i v , o ) v 6 . 30 4 i d d d n i e s a e r c n ii d d t u p n i r e p v h i v = d d , v 6 . 0 - v t a s t u p n i d d d n g r o 0 0 4 notes: 1. not guaranteed 2. duration of test must not exceed 1 second with only 1 output tested at a time. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued from previous page)
6 ps8355a 11/23/98 pi74alvtc16373 16-bit transparent d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 dc characteristics (1.8v v dd 2.3v) electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued from previous page) n o i t p i r c s e ds r e t e m a r a ps n o i t i d n o cv d d . n i m. p y t. x a ms t i n u v h i e g a t l o v t u p n i l e v e l h g i h 3 . 2 - 8 . 1 x 7 . 0v d d v v l i e g a t l o v t u p n i l e v e l w o l v x 2 . 0 d d v h o e g a t l o v t u p t u o l e v e l h g i h i h o 0 0 1 - = m a 8 . 1 v d d 2 . 0 - i h o a m 6 - =4 . 1 v l o e g a t l o v t u p t u o l e v e l w o l i l o 0 0 1 = m a2 . 0 i l o a m 6 =3 . 0 i i t n e r r u c e g a k a e l t u p n iv i v = d d d n g r o3 . 20 . 5 m a i z o e g a k a e l t u p t u o e t a t s - 3v o 6 . 3 = v8 . 10 1 i f f o t n e r r u c e g a k a e l f f o - r e w o pv i v = o 6 . 3 v0 0 1 i l d o w o l t n e r r u c t u p t u ov n i = v h i r ov , l i v o =v 9 . 0 ) 2 ( 8 . 1 0 57 3 1 a m i h d o h g i h t n e r r u c t u p t u ov n i = v h i r ov , l i v o =v 9 . 0 ) 2 ( 4 1 -4 3 - i d l o h ) 1 ( t n e r r u c d l o h s u b s t u p t u o b r o a v i 4 . 0 = 8 . 1 0 5 m a v i 3 . 1 =0 5 - i d d t n e r r u c y l p p u s t n e c s e i u q v i v = d d d n g r o0 2 v d d v ( i v , o ) v 6 . 30 2 i d d d n i e s a e r c n ii d d t u p n i r e p v i v = d d , v 6 0 - v t a s t u p n i r e h t o d d d n g r o 0 0 4 notes: 1. not guaranteed 2. duration of test must not exceed 1 second with only 1 output tested at a time.
7 ps8355a 11/23/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74alvtc16373 16-bit transparent d-type latch with 3-state outputs ac electrical characteristics note 1. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. the specification applies to any outputs switching in the same direction, either high or low (t oshl ) or low to high (t oslh ). ac setup requirements capacitance l o b m y sr e t e m a r a p t a c , c 5 8 + o t c 0 4 - = l r , f p 0 5 = l 0 0 5 = w s t i n u v d d v 3 . 3 = v 3 . 0 v d d v 5 . 2 = v 2 . 0 v d d v 8 . 1 = . n i m. x a m. n i m. x a m. n i m. x a m t , h l p t l h p q o t d , y a l e d p o r p5 . 05 . 20 . 12 . 35 . 10 . 4 s n t , h l p t l h p q o t e l , y a l e d p o r p0 . 11 . 35 . 12 . 40 . 25 . 4 t h z p t , l z p e m i t e l b a n e t u p t u o0 . 11 . 35 . 17 . 40 . 25 . 4 t z h p t , z l p e m i t e l b a s i d t u p t u o5 . 17 . 35 . 15 . 30 . 20 . 5 t l h s o t h l s o w e k s t u p t u o o t t u p t u o ) 1 ( 5 . 05 . 05 . 0 l o b m y sr e t e m a r a p t a c , c o 5 8 + o t c o 0 4 - = l r , f p 0 5 = l 0 0 5 = w w w w w v d d v 3 . 0 v 3 . 3 =v d d v 2 . 0 v 5 . 2 =v d d v 8 . 1 = . n i m. p y t. n i m. p y t. n i m. p y ts t i n u t u s e l o t d , e m i t p u t e s5 . 000 s n t h e l o t d , e m i t d l o h8 . 05 . 00 . 1 t w h g i h , h t d i w e s l u p e l5 . 15 . 15 . 1 l o b m y sr e t e m a r a ps n o i t i d n o c t a c 5 2 + = l a c i p y ts t i n u c n i e c n a t i c a p a c t u p n iv d d v , v 3 . 3 r o v 5 . 2 , 8 . 1 = i v r o v 0 = d d 6 f p c t u o e c n a t i c a p a c t u p t u ov i v r o v 0 = d d v , d d v 3 . 3 r o v 5 . 2 , v 8 . 1 =7 c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p v i v r o v 0 = d d z h m 0 1 = f , v d d v 3 . 3 r o v 5 . 2 , v 8 . 1 = 0 2
8 ps8355a 11/23/98 pi74alvtc16373 16-bit transparent d-type latch with 3-state outputs 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 test circuits and switching waveforms parameter measurement information (v dd = 1.8v - 3.6v) setup, hold, and release timing pulse width switch position propagation delay enable disable timing t s e t1 s t d p n e p o t z l p / t l z p x 2 v d d t z h p / t h z p d n g data input t h v dd t su 0v timing input v dd 0v v dd/2 v dd/2 low-high-low pulse t w high-low-high pulse v dd 0v v dd 0v v dd/2 v dd/2 input opposite phase input transition t plh t phl t plh t phl v dd 0v v dd v ol v dd 0v output v dd/2 v dd/2 v dd/2 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2ns, t f 2ns, measured from 10% to 90%, unless otherwise specified. d. the outputs are measured one at a time with one transi- tion per measurement. pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com output control (active low) output waveform 2 s1 at gnd (see note b) t pzl t plz v dd 0v v dd v ol 0v output waveform 1 s1 at 2xv dd (see note b) +0.15v -0.15v v oh v dd t phz t pzh v dd/2 v dd/2 v dd /2 c l r 1 500 w 50pf from output under test gnd 2 x v dd open (see note a) r l 500 w
|
